A 2.8 mW/Gb/s quad-channel 8.5-11.4 Gb/s quasi-digital transceiver in 28 nm CMOS

Ali Nazemi, Hassan Maarefi, Burak Catli, Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Mohammed Abdul-Latif, Yang Liu, Jaehyup Kim, Afshin Momtaz, Namik Kocaman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

A SerDes operating from 8.5 to 11.4 Gb/s using nearly all CMOS digital circuits is presented. The transmitter achieves up to 1 Vdpp output swing with a DDJ as low as 2.7 ps. The receiver achieves an input sensitivity of less than 17 mVdpp. The chip is capable of transmitting and receiving data on an FR4 channel with 21 dB loss at Nyquist at a BER < 10-12. The power consumption per Tx/Rx pair is 28.5 mW, and the active area is 0.047 mm 2 in 28 nm CMOS. The chip reports the minimum SerDes area in the published literature.

Original languageEnglish (US)
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
PagesC276-C277
Publication statusPublished - Sep 17 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: Jun 12 2013Jun 14 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period6/12/136/14/13

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ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Nazemi, A., Maarefi, H., Catli, B., Ahmadi, M. R., Fallahi, S., Ali, T., ... Kocaman, N. (2013). A 2.8 mW/Gb/s quad-channel 8.5-11.4 Gb/s quasi-digital transceiver in 28 nm CMOS. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers (pp. C276-C277). [6578693] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).