A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications

Burak Catli, Ali Nazemi, Tamer Ali, Siavash Fallahi, Yang Liu, Jaehyup Kim, Mohammed Abdul-Latif, Mahmoud Reza Ahmadi, Hassan Maarefi, Afshin Momtaz, Namik Kocaman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

An 8.0 GHz to 12.2 GHz PLL with a capacitor multiplier-based active loop filter is designed in a 28 nm digital CMOS process. A passive loop filter-based version of the PLL is also implemented for comparison. While the PLL area is comparable to that of digital PLLs, the PLL performance is as good as that of an analog PLL that employs a passive loop filter. The capacitor multiplier-based active loop filter PLL has a jitter performance of 198 fs (rms), while its passive loop filter-based counterpart shows a jitter performance of 195 fs (rms). The PLL occupies 0.093 mm2 and consumes 15.5 mA at 1.0V.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781467361460
DOIs
Publication statusPublished - Nov 7 2013
Externally publishedYes
Event35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013 - San Jose, CA, United States
Duration: Sep 22 2013Sep 25 2013

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Conference

Conference35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
CountryUnited States
CitySan Jose, CA
Period9/22/139/25/13

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ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Catli, B., Nazemi, A., Ali, T., Fallahi, S., Liu, Y., Kim, J., ... Kocaman, N. (2013). A Sub-200 fs RMS jitter capacitor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications. In Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013 [6658471] (Proceedings of the Custom Integrated Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2013.6658471