A second version ASIC for front-end detector readout, TIMPIC-II, has been developed for Solid-State Photomultiplier (SSPM) based PET applications. It uses the previously developed and evaluated time-based-readout (TBR) architecture. However, several major changes have been made to make TIMPIC-II more flexible and suited for PET applications, including adding a common energy trigger to select the true events and using a constant width integrator to improve linearity. A special logic unit is added to combine the energy and the timing pulses into one output signal that reduces half of the output pins. A 16-channel chip has been designed and fabricated with 0.35μm 2P4M CMOS technology. The die area is 3mm × 3mm, and the chip is provided in a compact 14mm × 14mm BGA package. TIMPIC-II initial evaluated result shows that the trigger and TBR with control logic function works as designed. And the ASIC specifications including linearity, intrinsic noise and timing jitter, etc. are well achieved as the linear regression R > 0.999 in full dynamic range, intrinsic energy resolution is better than 0.1% FWHM of 500pC and the timing jitter standard deviation is 100-300ps for different input signal range. This ASIC is also tested and used for a PET front-end detector module with FPGA-based TDC and acquisition.